1. Field of the Invention
The present invention relates to a memory device, and method of operation of such a device, and in particular to techniques for controlling a write operation within a memory device.
2. Description of the Prior Art
As process geometries shrink in modern data processing systems, the variability in the operating characteristics of the individual circuit elements increases. Considering as an example a memory device consisting of an array of memory cells, it will be understood that each memory cell will typically consist of a number of electronic components such as transistors, and the variability in those individual components significantly increases as process geometries shrink. To ensure correct operation of the memory device, it is necessary to control the operation of the memory device having regards to the worst case characteristics of the memory cells within the device.
Furthermore, there is an increasing desire to operate data processing systems at lower and lower supply voltages, and as the supply voltage decreases, reliability issues due to the variations in the individual components become more prominent.
Considering the steps required to perform a write operation to a number of memory cells within a memory device, this typically involves asserting a write word line signal to the appropriate row of the memory array so as to enable the addressed memory cells in that row, such that they can then store the required write data in accordance with values provided on their bit lines. The write word line signal is typically provided as a pulse, with the width of that pulse being set having regards to the worst case memory cell within the device, i.e. the width of the pulse has to be long enough that the memory cell in the device which takes the longest to store write data has sufficient time to correctly store the write data.
It is known to use techniques such as dynamic noise margin techniques in order to characterise the stability of cells within a memory device, and as a result of that characterisation to determine an appropriate write word line pulse width that will take account of the worst case cell within the device. For example, the article “Dynamic SRAM Stability Characterization in 45 nm CMOS” by S Toh et al, 2010 Symposium on VLSI Circuits, describes the use of a dynamic noise margin method that uses critical word line pulse width to estimate SRAM cell stability more precisely. However, it is still complicated to determine the appropriate word line pulse width to use for any particular memory device. During a write operation of a memory device such as an SRAM memory, if a write word line pulse width is set not long enough, this will cause write failures within the memory device, whilst if the write word line pulse width is too long, this will limit the operation frequency of the memory device. In general, a sufficient design margin is required to overcome the worst case scenario, as discussed for example in the article “Worst-Case Design and Margin for Embedded SRAM” by R Aitken et al, 2007 Design, Automation and Test in Europe.
However, as discussed above, technology scaling and/or supply voltage reduction that is prevalent in many modern day systems, leads to a requirement for the margin to be made larger and larger. As a result, such larger margins have a very significant impact on performance, and in turn are becoming one of the most challenging issues in the future design of memory devices.
One known technique for seeking to reduce variation and increase operating speed is referred to as word line boosting, described for example in the article “On the Efficacy of Write-Assist Techniques in Low Voltage Nanoscale SRAMs” by V Chandra et al, 2010 Design, Automation and Test in Europe. By increasing word line voltage, the access transistors of the memory cells are overdriven, causing the memory cells to be written more strongly, and as a result increasing operating speed and reducing margin. However, in modern memory devices, it is often the case that not all of the memory cells connected to a particular word line are actually being written in any particular clock cycle, those memory cells not being written being referred to as half selected memory cells. If the word line voltage is increased, this increases the possibility that during the write operation the data in these half selected cells is corrupted (i.e. caused to flip state). Hence, whilst the word line boosting approach can increase operating speed and reduce the margin required for the write word line pulse width, it can cause data corruption in half selected cells, and accordingly the amount of word line boosting has to be carefully managed. Further, over time, the exposure of the word lines to an increased voltage can give rise to various reliability problems within the memory device.
Accordingly, it would be desirable to provide an improved technique for performing write operations on addressed memory cells within a memory device, that would enable a reduction in the write word line pulse width margin.